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International Journal of Electronics Signals and Systems (IJESS)
ISSN:2231- 5969

Volume 3 Issue 2
   Table of Contents  Editorial

SLNO.

TITLES AND AUTHORS

PAGE NO.

1.

Self adaptive effective aperture for multi antenna set-ups in faded wireless channels
Parismita a. Kashyap, kandarpa kumar sarma

1-7

2.

Speech recognition based embedded control system
Parvez, prof. V. K. Joseph

8-14

3.

Design And Implementation Of Turbo Coder For LTE On FPGA
Gooru Santosh, Dr. S. Rajaram

15-19

4.

Visual Aid System Based On Image Matching And Ultrasound Sensor Principles For Blind Persons
A. Dhanshri, K. R. Kashwan

20-27

5.

Autonomous reconfiguration of ip core units using BLRB algorithm
B.Harikrishna, Dr. S. Ravi

28-32

6.

Design of Improved Performance Rectangular Microstrip Patch Antenna using Peacock and Star Shaped DGS
Preet Kaur, Rajiv Nehra, Manjeet Kadian, Dr. Asok De, Dr. S.k. Aggarwal

33-37

7.

Design of a 500MHz, 4-bit Low Power ADC for UWB Application
Santosh Kumar Patnaik, Dr. Swapna Banerjee

38-43

8.

Design and Implementation of Multi-Sensor Robot For Rigid Industrial Environment
S.K. Moula, Mr. J. Amarendra

44-47

9.

Miniature Improved Carry Select Adder with Advance Features and Power Requirements
D. Krishna Naik, Dr. V.Vijayalakshmi

48-52

10.

A Study of Power Line Interference Cancellation Using IIR, Adaptive and Wavelet Filtering in ECG
Imteyaz Ahmad, F. Ansari, U.K. Dey

53-55

11.

Cancellation of Motion Artifact Noise and Power Line Interference in ECG Using Adaptive Filters
Imteyaz Ahmad, F. Ansari, U.K. Dey

56-58

12.

Simulation and Analysis of 3T and 4T CNTFET DRAM Design in 32nm Technology
N. Somorjit Singh, Dr. M. Madheswaran

59-65

13.

Offline Signature Verification Based on GLCM
Nagendra Babu P., K.Chaithanya Sagar, A.Surendra Reddy

66-72

14.

A Novel Feature Expansion Algorithm for Nonrigid CT/MRI Brain Image Registration
Harsha Vardhan.N., S.Asif Hussain

73-80

15.

A Low Power New Data Compression Algorithm for Wire/Wireless Sensor Networks Using K-RLE
V. Krishnan, Mr. R. Trinadh

81-87

16.

A New Low Power Technology For Power Reduction in SRAMís Using Read Stability With Reduced Transistor Count for Future Caches
K. Hari Krishna, P. Hareesh

88-91

17.

CRBBE Algorithm for Low Power and High Speed Multiplier Design
K. Sanjeeva Rao, A. Ram Kumar

92-96

18.

Multi-Degree Smoother for Low Power Testable Digital System Design Using BS-LFSR and Scan-Chain Ordering Techniques
V. Suryanarayana, K. Miranji

97-104

19.

Decoupling Logic Based SRAM Design for Power Reduction in Future Memories
M. Premkumar, Ch. Jaya Prakash

105-109

20.

Implementation of Multitrack Simulator in FPGA for ESM System
J. Mohan Prithvi, D. Ajay Kumar

110-113

21.

STDFF a Pass Transistor Based Flip Flop Design for Efficient Integrated Circuits
G. Lakshmi Praneetha, P. Hareesh

114-117

 

 

 

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