IJEEE

EFFECTS OF A BARRIER LAYER IN INGAAS CHANNEL MOSFETS FOR ANALOG/ MIXED SIGNAL SYSTEM-ON-CHIP APPLICATIONS

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Abstract

Addition of a barrier layer in an InGaAs MOSFET, which shows promise for high performance logic applications due to enhanced electron mobility, further improves the electron mobility. We report, for the first time, a detailed investigation of the impact of different barrier layers on the analog performance of an InGaAs MOSFET. The device parameters for analog applications, such as transconductance (gm), transconductance-to-drive current ratio (gm/IDS), drain conductance (gd), intrinsic gain, and unity-gain cutoff frequency (fT) are studied with the help of a device simulator. A barrier layer is found to improve the analog performance of such a device in general; with a double-barrier layer showing the best performance.

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